This invention relates to data processing systems and more particularly relates to techniques for interconnecting the buses which link data processor units with system resource units or other processor units.
A system resource unit is a device capable of communicating by means of digital data with another system resource unit or a processor unit. A processor unit is a device which can control a switch means either by a program stored in the processor unit or by a command received from another processor unit. Of course, a processor unit is a more specific type of resource unit.
The general concept of connecting a number of processor units or system resource units to form an integrated computing system has been under study in the field of data processing architecture for some time. One of the problems impeding the development of such architecture has been the lack of a versatile and comprehensive means for interconnecting the units of the system. In the past, the units have generally been connected by buses that are physically fixed in relationship to the various units. Although this arrangement may be adequate for some uses of the system, it lacks the flexibility required for certain applications, such as the interconnection of processor units or resource units used to control aircraft.
The applicant has found that an aircraft control system employing multiple processor or resource units requires a variety of interconnection features. For example, the system requires executive control of all units to effect scheduling, resource allocation and general system control. Since a number of units might be working on a single functional or logical process, there is a need for high speed communication between small groups of units. However, the number of units in the groups and the composition of the groups change from time-to-time. There is also a need for logical process intercommunication. For example, certain types of data, such as aircraft state vector, need to be communicated between groups of units operating on different functional or logical problems. In addition, since individual units may break down from time-to-time, there must be provision for fault detection and reconfiguration of the units to minimize aircraft malfunction due to the break down.
In order to achieve the foregoing objectives, the applicant has invented an improved bus interconnection technique for a data processing system including multiple processor or resource units. According to this technique, the units may be operated individually, or they may simultaneously be in communication with each other. In addition, the techinque has the capability of communicating certain kinds of data to all of the units and simultaneously communicating other kinds of data to only certain units of the overall system.
According to one feature of the invention, the data processing system comprises first and second resource units and a processor unit including first, second and third interfaces respectively. In order to provide communication between the units, a first bus is connected to the first interface, and a second bus is connected to the second interface. Switch means that are switchable into a number of states provide versatile combination of unit interconnections. For exmple, the switch means can be switchable into a first state for connecting the first bus to the third interface so that the first resource unit and the processor unit communicate over the first bus. Alternatively, the switch means can interconnect the second bus to the third interface so that the second resource unit and the processor unit communicate over the second bus. The first and second buses can also be connected together and simultaneously disconnected from the third interface so that the first and second resource units communicate with each other while the processor unit operates independently. Likewise, the first and second buses can be connected together and to the third interface so that the first and second resource units and the processor unit simultaneously communicate with each other.
According to another feature of the invention, the first and second resource units and the processor unit can each include first, second and third global interfaces respectively. In such a system, a global bus can be provided with a switch which simultaneously connects the first, second and third global interfaces to the global bus, so that each of the units may receive or transmit messages over the global bus or over the first or second buses.
The advantages of the foregoing system will be apparent to those skilled in the art. By using such techniques, multiple units may be interconnected in a wide variety of useful networks to maximize the speed and convenience with which data is processed. In addition, the interconnection of the units may be altered under program control to accommodate changes in the type of information being processed.